A 0.14-mm2 Mixed-Type True-Time Delay Circuit Based on Slow-Wave Transmission Lines Covering 52.8ps for 5G/B5G Carrier Aggregation

This paper presents a compact passive mixed-type true-time delay (TTD) circuit for wideband phased-array systems. The proposed circuit cascades a reflective TTD and two APN-based TTDs. In the reflective TTD, an ultra-compact monolayer coupler is adopted to reduce gain and delay variation. Furthermore, slow-wave transmission lines (SW-TLs) are also utilized in this work to improve the overall area efficiency. The proposed circuit is implemented in a 65-nm CMOS process. It covers a frequency band of 21–31 GHz. The measured delay coverage is 52.8 ps with a tuning step of 4.8 ps. The corresponding RMS delay error and gain error are less than 1.7 ps and 0.63 dB, respectively. Thanks to ultra-compact coupler and the SW-TLs, the chip core area is only 0.14-mm2. A delay-per-area of 377.14 ps/mm2 is realized by this work.