A Cryo-CMOS Fractional-N PLL in 22 nm FDSOI operating at 6 K for Trapped-Ion Quantum Computer Applications

This paper presents a fractional-N charge-pump phase-locked loop (CP-PLL) operating at cryogenic temperatures (CT) down to 6 K. The PLL, generating signals in the frequency range around 2.3-2.7 GHz, is intended as a reference source in microwave signal generator for a trapped-ion quantum computer operating with Be ions. Using a third-order MASH Delta Sigma modulator (DSM) the PLL achieves a highly competitive FoM of -245 dB. The circuit exhibits the highest fractional spur suppression among the recently reported cryogenic PLLs, as well as the lowest chip area.