A Low-Jitter Dual-Edge Sampling PLL Based on Joint Optimization of Injection and Ring-VCO

This paper presents a ring voltage-controlled oscillator (RVCO)-based sampling phase-locked loop (PLL) that achieves low in-band phase noise and low jitter within an extremely small area. The proposed dual-edge sampling scheme employs implicit oversampling to effectively double the gain without requiring calibration after the multi-modulus divider (MMD), thereby reducing unnecessary area and power overhead. To further suppress noise, a reference-to-RVCO injection with joint optimization of injection and RVCO (JOIR) is proposed to enhance the suppression of RVCO's phase noise under tight area constraints. Fabricated in a 40-nm CMOS process, the proposed PLL occupies a compact 0.019 mm² active area. It achieves an in-band phase noise of --121.4 dBc/Hz at a 100 kHz offset from a 5.4 GHz output, and the rms jitter integrated from 1 kHz to 40 MHz is 394.5 fs.