A 0.48W/mm² High-Power-Density D-Band Power Amplifier in 250-nm InP HBT Process

This paper presents a compact, high-power-density D-band power amplifier (PA) in a 250-nm InP HBT technology. The PA utilizes a three-stage differential unit cell based on a common-base (CB) topology with capacitive degeneration and compact slotline-based matching networks. An 8-way slotline-based series-parallel combiner (SSPC) with ground slots is used to combine four differential unit cells, thereby minimizing load-admittance imbalance among the unit cells while reducing passive loss. The PA achieves a peak gain of 19.4 dB and a 3-dB bandwidth of 24.3 GHz. Large-signal measurements demonstrate a saturated output power (Psat) of 18.7–23.6 dBm, an output 1-dB compression point (OP1dB) of 13–21.2 dBm, and a maximum power-added efficiency (PAEmax) of 6.9–20.1% across 127–160 GHz. The chip occupies 0.47 mm² with a 0.21 mm² core area, achieving a power density of 0.48 W/mm² — the highest reported to date for D-band InP PAs. These results demonstrate the effectiveness of compact CB-based architecture and low-loss SSPC topology for scalable D-band phased-array transmitters.