A 265–317-GHz Frequency Doubler with an Asymmetric Marchand Balun Achieving >40-dBc Fundamental Rejection in 65-nm CMOS

This work presents a 265–317-GHz 2-way frequency doubler with a wideband asymmetric Marchand balun, implemented in 65-nm CMOS. The proposed balun is realized by asymmetrically adjusting the coupling coefficients and electrical lengths of the two coupled-line sections and incorporating an output phase-compensation segment. EM simulations show amplitude- and phase-imbalance bandwidths (±1 dB / ±1°) of 30–240 GHz and 116–240 GHz, respectively. Leveraging the asymmetric balun and the 2-way combining architecture, the doubler achieves a maximum output power of −1.2 dBm at 298 GHz, a 3-dB bandwidth of 52 GHz (265–317 GHz), and more than 40-dBc fundamental rejection over 250–300 GHz, while consuming 410 mW from a 1.2-V supply.