A 21–27-GHz Frequency Quadrupler in 0.13µm SiGe BiCMOS with 0-dBm POUT and 40-dBc HRR for Wideband 5G Applications

A 21–27-GHz frequency quadrupler in 0.13µm SiGe BiCMOS technology with 0-dBm output power (POUT) and 40-dBc harmonic rejection ratio (HRR) is presented. A method for load-pull based output network design is introduced for co-optimizing HRR and POUT; as a result, the design achieves flat and exceptionally high HRR and POUT across 25% bandwidth (BW) and a wide input power (PIN) range. System integration of LO multipliers in wideband scalable 5G phased-array transceivers (TRX) is discussed. In this context, measurements of 64-element wideband 5G phased-array TRXs including and excluding the quadrupler are presented to further demonstrate the minimal impact of the quadrupler on the output spectrum. The measured total radiated power (TRP) of spurious emissions across the POUT range of the phased-array is < -20dBm/MHz, well below the 3GPP 5G FR2 requirement of -13dBm/MHz. The quadrupler design has the highest HRR performance reported among wideband mmWave quadruplers and demonstrates, for the first time, the impact of the LO frequency multiplier on the performance of a wideband phased-array system.