Substrate-Dependent Loss in High-Stacked Switch Branches in 28 nm FD-SOI CMOS on Standard and High-Resistivity Substrates

This work analyzes loss mechanisms in stacked switch-branch structures implemented in 28 nm FD-SOI CMOS on several substrates, from standard-resistivity silicon (10 Ωcm) to high-resistivity (HR > 1 kΩcm). Switch branches with 1–8 stacked devices were measured up to 40 GHz, and Π-network extraction was used to separate series-channel losses (Ron-total) from substrate-induced shunt losses (Gsh). While the total series resistance is kept constant by FET-resizing across stack levels, the shunt conductance increases strongly with stack count and becomes the dominant loss mechanism on standard substrates, whereas its impact is negligible on HR. The substrate-dependent stacking limit predicted by the Π-model analysis is confirmed through two complete SPDT switches (3- and 12-stack), whose measured insertion losses support the predicted trends. These results demonstrate that substrate-induced shunt loss is a primary constraint for scalable, high-power switch design.