Mixed-Mode Distributed Equivalent Circuit Model of PCIe 7.0 Connector for Accelerating 128 GT/s PAM4 Signal Integrity Analysis

This work presents the development of a mixed-mode distributed physical-based transmission line (mm-dPBTL) equivalent-circuit model for the Peripheral Component Interconnect Express 7.0 (PCIe) low-profile fast-pass input/output (Lopro FPIO) connector. Separate distributive circuits are constructed for multi-pair differential mode (DM) and common mode (CM), while mutual couplings between propagation paths, signal stubs, and ground cavities (GC) are incorporated to capture baseline performance and resonance mechanisms in mixed-mode S-parameters (Sdd, Sdc, Scc) up to 64 GHz. Comprehensive bandwidth evaluation supports channel analysis for 128 GT/s PAM4 signalling in PCIe 7.0 links, exhibiting less than 2% deviation in eye height (EH) and eye width (EW). In comparison to HFSS 3D simulation, the 1D mm-dPBTL model accelerates signal integrity (SI) analysis by reducing 1000x simulation time as well as providing physical insight of crosstalk degradations.