Sub-10-GHz Cryo-CMOS LNAs Achieving Up to 0.07-dB Average NF Thanks to Back Biasing for Qubit Readout in 28-nm FD-SOI

This paper presents cryogenic CMOS inverter-based low noise amplifiers (LNAs) for highly integrated quantum readout electronics. The circuits are fabricated in a 28-nm FD-SOI process. The LNAs consist of three stages: a first inverter stage for noise optimization, a second inverter stage for gain enhancement and a last output buffer stage for impedance matching. Four versions have been designed to cover all qubit readout sub-10-GHz scenarios. The LNAs are measured on a cryogenic on-wafer probe station at room temperature (RT: 300K) and at cryogenic temperature (CT: 4K). Thanks to the use of the back gate, the proposed circuits achieve, depending on the version, a noise figure (NF) of 1.2–2.6 dB and 0.13–0.54 dB at 300K and 4K, respectively. By pushing further the back gate voltage, a minimum NF of 0.07 dB at 4K is attained, corresponding to an ultra-low noise temperature of 4.7K.