MOSFET Modeling with the sEKV Model for the Design of Cryo-CMOS Circuits

The lack of compact models in commercial PDKs that have been validated at cryogenic temperature (CT) makes the design of cryo-CMOS circuits a real challenge. The designs can unfortunately not be verified by simulation at CT which can lead to costly re-spins and delays. The simplified-EKV (sEKV) model with its only four parameters has been successfully validated at CT for several advanced CMOS technologies, including bulk, FDSOI and FinFET. Additionally, it has been shown that the normalized  characteristic and the Fano noise suppression factor are almost invariant to temperature. The sEKV model together with the inversion coefficient as main design variable and the gm/ID design methodology can therefore guide the designer in optimizing his circuit to operate at CT. This presentation will give a state-of-the-art of the recent progress made in the characterization and modeling of the MOSFET for operation at CT. It will cover the following topics: 1) DC modeling, 2) small-signal modeling, 3) RF characterization and modeling and 4) noise. A particular focus will be given to the sEKV model and the related design methodology for analog and RF circuits.