Calibration-Free DSM Noise Suppression in Analog Frequency Synthesizers

A major advantage of a digital PLL (DPLL) over an analog PLL (APLL) is its ability to cancel quantization noise from the delta-sigma-modulator (DSM) robustly. This allows the loop bandwidth to increase thereby suppressing the noise contribution of the VCO and improving figure-of-merit (FOM). The cost of this improved performance is complexity, with the introduction of sophisticated time-to-digital converters (TDC) or digital-to-time converters (DTCs). Although equivalent DSM noise cancellation can be accomplished in the analog domain, it has proven sensitive to mismatch and has not seen widespread adoption. Instead of analog or digital cancellation, this talk will give an overview of alternative calibration-free methods for DSM noise suppression in APLLs. First, a low-power topology is discussed that eliminates DSM quantization noise by overclocking the DSM. Importantly for many applications, the topology uses a standard XTAL square-wave reference. Second, the advantages of a high-reference source (such as an FBAR oscillator) are explored through two designs: a standard high-reference topology that naturally employs DSM overclocking, and an offset APLL that suppresses DSM noise through loop gain reduction. Finally, a high-performance mm-wave system is outlined that combines an integer PLL with an offset mm-wave APLL to achieve state-of-art performance while using a sub-100MHz reference.