A Flip-Chip W-band On-off Keying Receiver in 90-nm CMOS
This paper presents a W-band on-off keying receiver in a standard 90-nm CMOS technology. The CMOS chip is flip-chip assembled on an integrated-passive-device carrier. The receiver includes a wide-band low-noise amplifier, a dual gain-boosted envelope detector, and an active feedback limiting amplifier. The demonstrated receiver achieves a data rate of 8 Gb/s under pseudorandom binary sequence of 27 – 1 with an on-off keying signal centered at 80 GHz. The sensitivity of the receiver is -29.7 dBm at a bit error rate of 10-12 and it consumes a dc power of 53 mW. The flip-chip integration facilitates wireline and wireless data links for millimeter-wave high-speed communications.