Design of a Low-Jitter Ring-Oscillator-Based Fractional-N Digital PLL

Modern SoCs for advanced wireless and wired transceivers are integrating an increasing number of phase-locked loops (PLLs) onto a single silicon die. 5G transceivers require multiple PLLs to support complex carrier aggregation schemes and MIMO, while the number of wired interconnect lanes continues to rise to meet the data throughput demands of AI computing. In this context, area-efficient PLL design has become increasingly important. From the perspective of silicon efficiency, ring-oscillator (RO)-based digital PLLs (DPLLs) offer clear advantages over conventional LC VCO-based analog PLLs. RO-based DPLLs are also more scalable with advanced CMOS technologies and can be implemented in CMOS nodes that lack high-quality metal layers for inductors. However, despite these advantages, their limited jitter performance has constrained their use in high-performance applications that demand ultra-low-jitter clock signals. This talk explores strategies for designing low-jitter RO-based fractional-N DPLLs and introduces advanced techniques to address the associated challenges.