Efficient Estimation of Stochastic Power Supply Noise Induced Jitter in CMOS Inverters via Knowledge-Based Neural Networks

In this paper, a knowledge-based neural network (KBNN) is developed for predicting jitter in the presence of stochastic power supply noise for CMOS inverter circuits. In the proposed hybrid approach, KBNN produces an efficient training using input data extracted from the both, analytical expressions for the stochastic power supply noise induced jitter (SPSIJ) as well as small number of data points from a computationally expensive but accurate circuit simulator. The proposed model demonstrates a reasonably accurate prediction of SPSIJ and yields significant speed-up as compared to a circuit simulator (HSPICE) for a case study with 45nm CMOS technology.