Low jitter frequency generation for 5G mm-wave cellular application
5G mm-wave cellular demands sub-100fs RMS jitter LO to support 256 QAM from 24.25GHz to 43.5GHz. This talk provides an overview of the advanced PLL and LO generation techniques for cellular handset. It starts with PLL topology and LO frequency plan. Then a DTC-based PLL design example is used to explain both critical PLL circuit design (VCO, phase detector, and etc.) and digital calibration techniques. The measured PLL RMS jitter is 83.4fs rms jitter in fractional-N mode, integrated from 10 kHz to 100 MHz, with a 76.8-MHz crystal oscillator reference. In low-power mode, the rms jitter degrades to 96.3 fs and the PLL FoM improves from -250.1 to -251.2dB, as the PLL power consumption reduces from 14.2 to 8.2mW. The measured fractional spurs are less than -70dBc for near-integer channels. It is implemented in a 14nm FINFET and is integrated in a 28/39GHz dual-polarized 5G phased-array transceiver IC.