A Fast and Highly-Linear Phase-Frequency Detector with Low Noise for Fractional Phase-Locked Loops

Phase-frequency detectors (PFD) for high-performance fractional phase-locked loops require high operating frequencies, high linearity, and low additive phase noise. Therefore, an XOR-based PFD architecture is presented, which is beneficial to achieve these requirements. It is implemented using SiGe:C heterojunction bipolar transistors with fT/fmax = 250/370 GHz and differential emitter-coupled logic gates. This PFD generates a pulse width modulated output signal and thus exhibits superior linearity without any dead zone. The PFD works up to 10 GHz, demanding a linear operation within a phase difference range of π rad. A low linearity error of less than 600 ppm up to 2 GHz is achieved. The PFD exhibits a very low input-referred additive phase noise with a floor of -163 dBc/Hz and a flicker noise corner of 13 kHz at an input frequency of 1GHz. The phase noise floor increases with the input frequency.