A Differential Rectifier Design Based on Impedance Splitting and Compression Technique For Achieving > 70% ηRF−DC Over 13 dBm Input Dynamic Power Range

This work proposes the design of a differential rectifier architecture using an impedance splitting technique to achieve a high-power conversion efficiency (PCE) performance over a wide input power range. The technique involves splitting the input impedance into two quasi-symmetrical high and low impedance rectifier branches such that the impedance profiles of the two branches vary inversely with each other across a wide input power range. The impedances of the individual branches are then compressed using an impedance compression technique to minimize the impedance variation across the low and high input power range to generate a high PCE over a wide power range. Measurement results show the proposed rectifier is able to achieve >60% PCE performance over a wide input power range of 17 dBm from 6 to 23 dBm, and a 13 dBm input power range from 9 dBm to 22 dBm is achieved for which the PCE is >70%.