1.9 GHz - 4.1 GHz CMOS Rectifier with Over 48% Efficiency using an Additional Resonance and CRT Reduction for Beamforming WPT System

This work presents the design of an ultra-wideband half-wave CMOS rectifier with maximum flat efficiency using an additional resonance at the output terminal. First, a diode model for high-frequency rectification is proposed by connecting a small capacitor between the drain and ground terminal to reduce clock recovery time (CRT). Second, maximum flat efficiency over a wide bandwidth is achieved by creating an additional resonance, which is realized by connecting the drain and the gate terminals with an inductor. The proposed design implemented in 0.18-µm CMOS technology achieves more than 48% conversion efficiency at 18 dBm input power in the frequency range from 1.9 GHz to 4.1 GHz, with an active circuit size of 0.5185 mm2.