Comparison of Wideband Low-Power H-Band Frequency Doublers with and without a Driving Stage in 22nm FDSOI CMOS

This paper presents a comparison of two low-power wideband frequency doublers operating above 220 GHz fabricated in a 22 nm FDSOI CMOS technology: chip 1 is a driverless frequency doubler; chip 2 integrates a pre-driver followed by a frequency doubler. The doubler core used in both chips is based on a pseudo-differential common source topology. The standalone doubler (chip 1) achieves a low measured conversion loss of 6.1 dB at 254 GHz. Along with a low DC power consumption PDC of 12.4mW at a Psat of 0.2 dBm, this amounts to an outstanding power efficiency ηtot of 5.6%. Additionally, the circuit occupies a minimal active chip area of only 0.046mm². To the best of the authors’ knowledge, this is the highest reported efficiency for a doubler in the frequency range above 200 GHz in advanced CMOS nodes. In addition to this, the second chip with a driver amplifier (chip 2) achieves a conversion gain (CG) of 3.4 dB and an efficiency of 2.2%. Both chips achieve a very good 3 dB bandwidth in excess of 24%.