Comparison of Wideband Low-Power H-Band Frequency Doublers With and Without a Driving Stage in 22 nm FDSOI CMOS

This paper presents two low-power wideband frequency doublers operating above 220 GHz fabricated in a 22 nm FDSOI CMOS technology: chip 1 is a driverless frequency doubler; chip 2 integrates the same doubler with a pre-driver. Both doubler cores are based on a pseudo-differential common source topology. Chip 1 achieves a low measured conversion loss of 6.1 dB at 254 GHz. With a DC power consumption of 12.4 mW this amounts to a high total power efficiency of 5.6%. Additionally, the circuit occupies an active chip area of only 0.046 mm². To the best of the authors' knowledge, this is the highest reported efficiency for a frequency doubler in the frequency range above 200 GHz in advanced CMOS nodes. In addition to this, chip 2 achieves a conversion gain (CG) of 3.4 dB and an efficiency of 2.2%. Both chips achieve a large 3 dB bandwidth in excess of 24%.