A 10 Gb/s 275 fsec Jitter Charge-Sampling CDR for QuantumComputing Applications

This letter presents the first clock and data recovery (CDR) system operating at 4.2 K designed for quantum com- puting applications. By considering the benefits and challenges of cryogenic operation, a dedicated analog CDR structure is employed so as to maintain high performance from 300 K down to 4.2 K. The CDR incorporates a new complementary charge-sampling based phase detector that achieves low-power and low- jitter. Fabricated in 40-nm CMOS, the proposed CDR operates at 10 Gb/s, achieving a recovered clock jitter of 260 fs and a jitter tolerance of 2 UIPP at a 5-MHz jitter frequency while consuming 4.7 mW at room temperature. At 4.2 K, the power consumption reduces to 3.1 mW with a recovered clock jitter of 275 fs and jitter tolerance of 0.85 UIPP at a 5-MHz jitter frequency, demonstrating its functionality for a high-speed cryogenic wireline link.