A D-Band ×15 Frequency Multiplier Chain in 45nm SiGe BiCMOS for Board-Level Packaged Array Applications

This paper presents a D-band frequency multiplier chain in 45nm SiGe BiCMOS technology. It achieves a high multiplication factor of 15 for large multi-chip packaged array applications. The design consists of a ×5 low-frequency multiplier, an interstage buffer, and a D-band tripler that directly drives the 50 ohm load. The bandwidth extension technique is applied with an electrically coupled transformer and a harmonic filter is implemented between the cascode transistors of the tripler to enhance the harmonic rejection ratio. The frequency multiplier chain operates from 123 GHz to 136 GHz with a saturated output power (Psat) of 1.1 dBm, a conversion gain of 2.9 dB, and a harmonic rejection ratio between 19.8 dB and 22 dB. The total DC power consumption of the design is 80 mW.