A DC-51.5 GHz Digital Step Attenuator with Sub-5 dB Insertion Loss and 3.1° RMS Phase Error

This paper presents an ultra-wideband and low loss digital step attenuator (DSA) with 15.5- /0.5-dB attenuation range/step. To reduce the insertion loss (IL), a merged attenuation cell is proposed to realize 4-/8-/12-dB attenuation. Moreover, a bridge-capacitor is adopted in the merged attenuation cell to expand the bandwidth of the proposed DSA while reducing the phase error between different attenuation states. The proposed DSA is fabricated with a 65-nm CMOS process with a compact core area of only 0.026 mm2. With measurements, over the entire operating bandwidth from DC to 51.5 GHz, it achieves an insertion loss of less than 5 dB and the root-mean-square (RMS) attenuation/phase errors of less than 0.25 dB/3.1°, respectively.