S-parameter-Based Simulation Technique and Crosstalk Suppression for Large-Scale Superconducting Quantum-Computing Chip Design

The increasing size of superconducting quantum computer chips necessitates a shift of evaluation methods in the chip design. 3D electromagnetic (EM) simulation suffers from increasing computation time with increasing model size, which makes the full-chip-scale EM analysis computationally intractable. To address this issue, we develop a technique to analyze circuit parameters of a large-scale superconducting qubit chip by combining the S-parameters simulated in small-scale 3D EM models. We have designed a 4-qubit unit cell for large-scale qubit device and evaluated the residual qubit-qubit coupling and control-line-to-qubit crosstalk for distant qubit pairs. We have also proposed guard structures around qubits to mitigate the nearest-neighbor crosstalk. While previous methods are applicable to chips containing at most ten qubits or so, our approach enables us to analyze more than a hundred qubits.