A 16-Way 115–129GHz High Power Amplifier with 20.9dBm PSAT and 17.6dBm P1dB in 40nm Bulk CMOS

This paper presents a 115–129 GHz power amplifier (PA) with a record PSAT in 40-nm bulk CMOS. The PA is based on a 4-stage differential common-source with cross-coupled capacitive neutralization with optimum device sizing and stage scaling with a transmission-line based low-loss 8:1 power combiner. On-wafer measurement shows 21.3 dB peak S21 and 14 GHz 3-dB bandwidth, with 20.9 dBm PSAT, 17.6 dBm P1dB and 7.6% power-added efficiency at 125 GHz at 1.2 V supply. The chip size of the PA is 1.34 mm² including pads, with 0.69 mm² core area. To the best of authors’ knowledge, the proposed PA shows the highest PSAT and P1dB for a D-band PA in CMOS.