A >22GS/s, 44dB SNDR Wideband 4×4 Time-Interleaved Sampling Front-End with Bulk-Driven Mismatch Calibration in 22nm FDSOI

This paper presents an ultra-wideband time-interleaving (TI) front-end (FE) sampler in 22nm FDSOI CMOS. It includes an isolating FE buffer driving 4 time-interleaved samplers and 2nd-level buffers operating at fs/4, each feeding 4 sub- Track and Holds (T&H) at fs/16. A low-jitter multi-phase on-chip clock generator (σrms ~40 fs), fed by a single differential reference clock, supports sampling speeds up to 32 GS/s resulting in an SNR of 48 dB at fin = 16 GHz. The FE incorporates on-chip TI time-skew and bandwidth mismatch calibration, while gain and offset mismatches are digitally calibrated off-chip. It achieves a peak SFDR of 54/49 dBc and SNDR of 46/44 dB for low and Nyquist frequencies at fs = 22 GS/s, while maintaining SFDR/SNDR above 38/35 dB at fs = 32 GS/s up to Nyquist. The on-chip time-skew calibration improves the SFDR by up to 16 dB. In addition, a novel bulk-node calibration technique addressing bandwidth mismatch is tested. The sampler operates from a triple supply (1.2 V/0.9 V/-0.6 V), consuming only 116 & 142mW at 22 & 32 GS/s, respectively.