A 0.9 pJ/bit 56Gb/s High-swing Tri-mode Wireline Transmitter with 6-bit DAC Controlled Tailless-CML Driver and Impedance Calibration Loop

This paper presents a tri-mode (PAM4, NRZ, Duobinary) transmitter which employs a tailless CML driver with an impedance calibration loop for achieving low power consumption and a high output swing, supporting a data rate up to 56Gb/s PAM4. The proposed DAC-controlled driver is capable of supporting a wide range of swing adjustments and achieving a high-resolution adjustable FFE. By introducing an impedance calibration loop with the assistance of an off-chip reference resistor, the transmitter is capable of mitigating the impedance mismatch under a high output swing caused by the utilization of tailless CML drivers. Fabricated and tested in 28nm CMOS process, the proposed transmitter with a total chip area of 0.536 mm² exhibits a power efficiency of 0.9pJ/bit and a vertical eye opening of 83 mV operating at 56Gb/s PAM4 under a -6 dB insertion loss condition.