An 86-90 GHz Adaptive Gain CMOS LNA with Linearity Enhancement & -6 dBm Blocker Tolerance

This paper presents a W-band adaptive gain low-noise amplifier to improve its IM3 rejection and blocker tolerance. The proposed design employs a current steering topology controlled by the adaptive bias (ADB) circuit and a novel coupler design for automatic gain control. The measurement results demonstrate a peak gain of 14.5 dB at 88 GHz with a dynamic gain control range of 13 dB and constant center frequency. The minimum measured NF is 7.6 dB at 88 GHz and <9.2 dB at the frequency of 86-90 GHz. Two-tone test measurements show 10 dB improvement in IM3 rejection, and the blocker test shows 15 dB improvement in SFDR compared to the LNA with the adaptive gain turned off. The chip was fabricated in TSMC 65nm CMOS, occupies a core area of 0.11 mm2, and consumes DC power of 37.2 mW when ADB is off and 40.8 mW when ADB is on.