A 6.5-GHz Low-Power Self-Interference Cancellation Receiver with Two-Stage Feedforward Technique and Automatic Gain Control Loop

This paper presents a two-stage feedforward self-interference cancellation (SIC) receiver designed for Frequency Division Duplexing (FDD) applications with low power consumption. The receiver employs a first-stage low-noise amplifier (LNA) to suppress noise contributions from the SIC path, enabling the second-stage circuits to operate with reduced power consumption. Additionally, an automatic gain control (AGC) loop and a passive-mixer-like transmission gate (PML-TG) are implemented to precisely control the amplitude and delay time without additional power overhead. Fabricated in TSMC 180nm CMOS technology, the proposed receiver, operating at 6.4–7.1GHz, achieves 30 dB of SIC at a 200-MHz offset for a signal bandwidth of 120 MHz. The design supports transmitter interference levels of up to 32 dBm while consuming only 24.1 mW of DC power.