A Wideband Dual-Mode Power Amplifier with Slotline-Based Series-Parallel Combiner in 28-nm Bulk CMOS Technology

This paper presents a wideband dual-mode power amplifier (PA) implemented in 28-nm bulk CMOS technology. The PA features a reconfigurable differential 4/8-way power combiner, utilizing a slotline-based series-parallel combiner (SSPC) and shunt switches, which supports two operation modes: high-power mode (HPM) and low-power mode (LPM). In HPM, the PA achieves 3-dB bandwidth of 27.9 GHz, with saturated output power (Psat) of 18‒19.3 dBm, 1-dB compression power (OP1dB) of 13.2‒15.1 dBm, and maximum power-added efficiency (PAEmax) of 20.4‒28.0% over the frequency range of 45‒70 GHz. In LPM, the 3-dB bandwidth is 30.8 GHz, with Psat of 13.6‒14.3 dBm, OP1dB of 9.2‒10.3 dBm, and PAEmax of 12.5‒17.1%. At 60 GHz, measurements using 64-QAM, 12-Gb/s signal demonstrate an rms error vector magnitude (EVM) of -25.3 dB, an average PAE (PAEavg) of 5.1%, and an average output power (Pavg) of 10.7 dBm in HPM, and -27.3 dB, 2.9%, and 5.3 dBm, respectively, in LPM.