400-GHz Concurrent Transceiver Imaging Pixel with Improved Noise Performance and Increased Injection Locking Range

A 400-GHz concurrent transceiver imaging pixel integrating an injection locking circuitry, VCO, SHM, TIA, and patch antenna within a (λ/2)^2 area and fabricated in the GF 22-nm FDSOI CMOS process achieves a measured locking range of 8.5 GHz by injection locking through the drain resonator of the VCO. The transmitter delivers a measured peak EIRP of -14.8 dBm and the receiver exhibits a minimum DSB NF of 33 dB. The system consumes 63.2 mW of DC power at 0.8-V VDD. This design has ~5.5 dB lower DSB NF and 9.5x higher locking range compared to the state-of-art (λ/2)^2 pixels operating at ~400 GHz.