A 127-to-156GHz 64QAM/256QAM Zero-IF CMOS Transceiver Chipset Achieving 47dB IRR and 17.8dBm Output Power

To address the demand for D-band applications requiring massive access with high modulation orders for users, a DC-coupled zero-IF transceiver chipset is proposed in this paper. To enhance the image rejection ratio, the transceiver adopts a wideband load-impedance robust stack coupler. To improve linearity, a biasing-free transconductance compensation mixer and an 8-way power combining power amplifier based on an enhanced magnetic coupling cavity with transmission line are proposed. Measurement results show that the system achieves a maximum IRR of 47dB and an output power of 17.8dBm. Additionally, the transmitter and receiver achieve data rates of 6Gbps for 64QAM and 1.6Gbps for 256QAM with a 2GHz variable gain amplifier operating bandwidth.