A 19.4-fsRMS Jitter 0.1-to-44GHz Cryo-CMOS Fractional-N CP-PLL Featuring Automatic Bleed Calibration for Quantum Computing

This paper presents the first cryogenic fractional-N charge-pump phase-locked loop (CP-PLL) operating at 4K, which can provide ultra-low-jitter clocks for data converters and precisely matched pump sources for the parametric amplifiers in superconducting quantum computers, thereby enhancing the accuracy of qubit control and the purity of the readout signal. Realized in a 28-nm CMOS, the CP-PLL prototype demonstrates stable operation across an ultra-wide temperature range from 4 K to 300 K, with an ultra-low jitter of 19.4 fs and a reference level of below −71 dBc, while offering a wide output frequency range from 0.1 to 44 GHz. Through the implementation of automatic bleed calibration, integer boundary spurs are further suppressed by an additional 40 dBc.