A Low-Power High-Dynamic Range Correlator Based on Parametric Multiplication and Integration

This paper presents an analog correlator for radar and communication applications. The proposed correlator incorporates a parametric mixer as the multiplier core achieving high dynamic-range while being low power due to the entirely passive architecture. The correlator unit prototype is fabricated in CMOS 22-nm FDSOI technology. The measured results show 55 dB hardware dynamic range, while supporting 1 GSym/s of template symbol rate with a scalable integration time. The correlator unit can further be extended to a multi-tap correlator network achieving 300 TOPS/W computing efficiency. The chip prototype is characterized in time and frequency, demonstrating its capability in applications such as time-of-arrival estimation and signal detection.