110-to-140GHz Frequency Tripler with 13% Efficiency, 7.2dBm Psat using Adaptive Biasing and 3rd Harmonic Boosting in 22nm FDSOI

This paper presents a high-efficiency D-band frequency tripler in 22 nm FDSOI CMOS. The operation point is chosen using drain current Taylor series derivation to boost the 3rd harmonic (H3) adaptively. The tripler core transitions for increasing input power (Pin) from compressive to expansive behavior thanks to the proposed biasing scheme. At low Pin of-10dBm the tripler achieves a peak conversion gain of 11dB thanks to step-up balun and capacitive over-neutralization. Yet, at high Pin of 4 dBm, the 5th-order nonlinearity boosts 3rd-harmonic and enables achieving 13% peak efficiency and Psat of 7.2 dBm.