Update Time of a Closed-Loop Digital Pre-Distortion on an RF System-on-Chip for Reconfigurable Transmitters
This paper presents a novel closed-loop digital pre-distortion (DPD) on a Xilinx RF system-on-chip (RFSoC). The architecture consists of a real-time DPD actuator implemented in the programmable logic (PL) of the RFSoC and an offline DPD update algorithm is executed on the ARM CPU in the RFSoC. This RFSoC directly synthesizes and captures the RF signal at the input and output of a 6-W GaN power amplifier evaluation board at 3.66 GHz. When the DPD is run iteratively, it is found that the CPU calculations are the main factor in the total time required to update the coefficients in the PL, with 427 ms needed for this memory-polynomial DPD with nonlinearity and memory orders of 6 and 3. When the DPD coefficients are updated, the DPD+PA is capable of 200 MHz instantaneous bandwidth at 3.6 GHz with a 35 dBc ACLR improvement as compared to the same signal without DPD.