TUMA26: Synchronizing systems with a high number of ADCs/DACs

Presentation Abstract
Synchronizing systems with a high number of ADCs/DACs is very difficult. New features implemented in an analog PLL and a synchronizer IC can help synchronize such systems. The PLL can introduce delays on both device clock and SYSREF to compensate propagation delays, while the synchronizer measures and compensates the round-trip delays that may happen on one or two wire connections. The seminar presents how such a system may be architected using a tree or a cascade approach and how the synchronization may be achieved.