Industry Workshops

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Venkata Vanukuru, Anurajan Hosagavi Puttaraju, Florinel Balteanu
GLOBALFOUNDRIES, Skyworks Solutions
Location
144C
Abstract

The research area of improving the performance, cost and size of 5G RF solutions and evolution to 6G is very active with many developments and it is one of the driving factors for semiconductor industry. Mobile cellular subscribers reached more than 6 billion in 2022 and 5G LTE brings high data capacity as low latency using sub-6GHz and mm-Wave spectrum. Mm-Wave up to 300GHz will play a major role in future 6G networks. The proliferation of worldwide smartphones has been in part possible due to increased computational power of CMOS technology in lower feature nodes as 3nm/7nm. This has made also possible to essentially enhance RF CMOS through digital signal processing (DSP) and digital calibration. The industrial workshop will cover 5G semiconductor technologies and architectures currently used in RF Front End Modules for cellular applications, the challenges for the 5G deployment as well the evolution to 6G.

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Salvatore Finocchiaro, Jeff Gengler, Markus Loerner, Florian Ramian, Wissam Saabe, Giorgia Zucchelli
Qorvo Inc., Rohde & Schwarz GmbH, AMCAD Engineering, MathWorks B.V.
Location
144C
Abstract

Communications standards such as 5G, WLAN, and SatCom as well as radar systems share the common trend towards higher frequencies and larger signal bandwidths. These trends impose tight requirements on transmitter linearity and power amplifiers efficiency. This workshop introduces a workflow to combine state-of-the-art PA measurements with behavioral models and prototypes for accelerating the design, optimization, and testing of linearization techniques. We will introduce recent trends in PA architectures and identify linearization techniques such as DPD, also taking into account load-pull effects. We will use hardware characterization and behavioral models to tradeoff design parameters and improve ACLR, EVM, and other metrics for 5GNR waveforms.

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Fouad Boueri, Dr. Larry Dunleavy, Matt Ozalas, Dr. Taylor Barton
Qorvo USA, Modelithics, Inc., Keysight Technologies, Univ. of Colorado
Location
144C
Abstract

This workshop will focus on successful model based GaN power amplifier design.  Advanced simulation approaches for achieving stable high efficiency amplifiers will be outlined.  This will include demonstration examples using Keysight Technologies’ Pathwave Advanced Design System software, along with accurate non-linear models for Qorvo GaN HEMT devices developed by Modelithics.  Tools and techniques to tackle design challenges, such as load-modulated design will be exemplified, as well as advanced stability analyses enabled by the new WS-probe, now available in ADS and embedded intrinsically in Modelithics Qorvo GaN models.

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Markus Lörner, Vince Mallette, Bryan Hosein, Sajjad Ahmed, Andre Engelmann, Marco Dietz
Rohde & Schwarz, MPI Corp., Focus Microwaves, Friedrich-Alexander-Univ. Erlangen-Nürnberg, Fraunhofer Research Institution for Microsystems and Solid State Technologies EMFT
Location
144C
Abstract

This workshop offers a deep dive, how precise load pull measurements support the optimization of RF power amplifiers in the D-band, a frequency range gaining momentum with its growing range of applications. Our session will center around a latest multi-stage power amplifier design operating in D-band. We will explore the distinctions and applications of passive versus hybrid load pull techniques, highlighting their roles in advanced measurement scenarios.
Collaborating with Friedrich Alexander Universität, we aim to present a comprehensive view of D-Band measurement challenges and solutions, addressing the practical and theoretical aspects vital for advancing in this evolving technology sphere.

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Robert Dandaraw, Judy Chui, Nico Blase
Analog Devices Inc.
Location
144C
Abstract

Join us in this workshop as we delve deep into the unique capabilities of the 20GSPS Apollo MxFE designed to enable high performance applications in X-Band Radar, Electronic Defense, and Instrumentation.  Learn how to leverage the on-chip hardened DSP feature set to add significant performance and lower power.  We will move beyond theory and share real world performance data, link to specific applications, and demonstrate the tangible impact on your next generation design.

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GAVIN FISHER
FORMFACTOR
Location
144C
Abstract

This talk will provide practical guidance on how best carry out full over temperature testing over multiple bands from 10 MHz all the way up to 1.1 THz using Wincal 5.0 software. 

We discuss benefits of a range of calibration techniques to optimise for test time and accuracy out and approaches to fully automate the data acquisition process. 

Recent techniques will be shown including Load pull to 170 GHz / 220 GHz and modulated testing with the Vector Component Analyser also to 170 GHz.

Workshop examples using Python / Wincal 5.0 will be provided along with supporting videos.

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Fabricio Dourado, Lei Xu
Rohde & Schwarz GmbH & Co KG, Fujikura Ltd.
Location
144C
Abstract

Phased array antenna modules (PAAM) need to operate at highest efficiency and still meet emissions and EVM requirements. A very high number of tests in power, frequency, waveform type, and modes are required. We will explain EVM impairments, techniques to diagnose root causes, and how to minimize the influence of test equipment. Then, review fundamentals of linearization, how to estimate if DPD is recommended, and present linearization results with gap analysis. The device under test will be a PAAM with at least 64 elements. Metrics include ACLR, EVM with and without demodulation, AMAM, AMPM, frequency response, and group delay.

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Michael Thompson, Sanam Vakili, Claudia Rosch, Kerry Judd, Ron Pongratz
Cadence Design Systems
Location
144C
Abstract

Simulation, DRC, LVS, ERC, EM, PI, Thermal, Minimal Routing, Performance, Price, and Manufacturability all complicate and restrict design space. Increasing design and system complexity require designers to consider individual designs within the larger system earlier in the design flow to maximize system performance. Cadence’s complete design flow with EM and Thermal Analysis is the backbone infrastructure needed for the next generation of designs. In this workshop, we will review the complete flow and introduce the audience to the ML capabilities within the Virtuoso flow to aid designers in satisfying increased requirements and exploring additional solutions.

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Nathan Altaffer
Keysight Technologies
Location
144C
Abstract

What happens to your chip’s performance when it is placed in the package?  How close is "too close" when placing multiple chips next to each other?  Does the loop height of that bondwire impact your RF output?  Does the void in board below your chip impact the operating bandwidth?  Wouldn't you like to know BEFORE you go to manufacturing?  Now you can! Here is a design flow that is built to do 3D Heterogenous Integration and it can be easily integrated with several EDA tools including ADS, Virtuoso, Custom Compiler, and Tanner.  

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Luc Langlois, Fabrício Dourado, Yoshiharu Fujisaku, Noam Levine
Avnet, Rohde & Schwarz GmbH & Co KG, Fujikura Ltd., The MathWorks
Location
144C
Abstract

Ever increasing demand for high throughput, low latency, and ultra reliability in wireless transmission requires accurate channel estimation under impairment conditions including Doppler shifts and noise. Traditional techniques for channel estimation in 5G NR involve known pilot sequences inserted into the transmission from which the rest of the channel response can be interpolated across all sub-carriers. 
 
This workshop will demonstrate a convolutional neural network (CNN) for channel estimation using OTA measurements through mmWave PAAM and AMD RFSoC-based 5G NR receiver in a CATR chamber. Training is accelerated by combining MATLAB with hardware-based channel impairments including AWGN and variable carrier-frequency offsets.