Back to IMS Schedule
Sun 15 Jun | 08:00 - 17:20
201
Frequency Synthesizer Design — from Fundamentals to Advanced Techniques
Wanghua Wu, Ahmed Elkholy, Teerachot Siriburanon, Salvatore Finocchiaro
Samsung Semiconductor, Inc., Broadcom, Univ. College Dublin, Qorvo
Frequency synthesizers are among the most critical blocks in wireless, wireline, and digital clocking applications. This workshop will cover both the fundamentals and the latest advances in frequency synthesis circuits and systems to efficiently generate LO signals with low phase noise, low spurious tones, and large modulation bandwidth. Prior-art techniques will be discussed in-depth, such as energy-efficient reference clocks, ultra-low phase noise voltage-controlled oscillators, digital PLL fundamentals, modern low-jitter fractional-N PLLs using both LC-oscillators and ring-oscillators. Special attention will also be given to pulling and spur mitigation techniques and PLL-based chirp generators for FMCW radar applications.
08:00 - 17:20
WSA-1 Reference Oscillator Architectures and Design Considerations
Danielle Griffith
Texas Instruments
08:00 - 17:20
WSA-2 Beyond All-Digital PLL for RF and mm-Wave Frequency Synthesis
Robert Bogdan Staszewski
Univ. College Dublin
08:00 - 17:20
WSA-3 Spur Analysis and Mitigation Techniques for Fractional Synthesizer
Michael Peter Kennedy
Univ. College Dublin
08:00 - 17:20
WSA-4 Calibration-Free DSM Noise Suppression in Analog Frequency Synthesizers
Dihang Yang
Broadcom
08:00 - 17:20
WSA-5 Design of a Low-Jitter Ring-Oscillator-Based Fractional-N Digital PLL
Jaehyouk Choi
Seoul National Univ.
08:00 - 17:20
WSA-6 (Voltage-Controlled) Oscillators with Ultra-Low Phase Noise
Andrea Mazzanti
Università di Pavia
08:00 - 17:20
WSA-7 Design and Performance Characterization of PLL-Based Chirp Generators for FMCW Radar Applications
Pratap Tumkur Renukaswamy
IMEC