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Mon 16 Jun | 13:30 - 15:10
207
High Speed and Domain Specific Data Converters
This session will cover the latest developments on high-speed ADCs, introducing time-interleaving, mismatch calibration and spur mitigation techniques. Machine learning circuits are also discussed for ADC calibration. Finally, the session closes on an ADC integrating mixed-signal multiplication stage for beamforming applications.
13:30 - 13:50
RMo3C-1 A 40GS/s 8bit Time-Interleaved Time-Domain ADC Featuring SFDR-Enhanced Sample-and-Hold Circuit and Power-Efficient Adaptive Pulse Generator in 28nm CMOS
13:50 - 14:10
RMo3C-2 A 12-Bit 6-GS/s Time-Interleaved SAR ADC with On-Chip Mismatch Calibration in 28nm CMOS Technology
14:10 - 14:30
RMo3C-3 Mostly Digital, Calibration-Free, Band-Pass Delta-Sigma Modulator Using Dual Time-Interleaved Noise-Shaping SAR ADCs
14:30 - 14:50
RMo3C-4 Circuits-Informed Machine Learning Technique for Blind Open-Loop Digital Calibration of SAR ADC
14:50 - 15:10
RMo3C-5 A 17mW 8-Element 2-Beam Hybrid Slepian Beamforming Receiver with SAR-ADC-Based Charge-Domain Multiply and Accumulation