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Tue 17 Jun | 13:30 - 15:10
203
PLLs and Frequency Multipliers
This session covers high performance PLL and frequency multiplier techniques. The first paper presents a high performance D-band double-sampling PLL with 35.1fs jitter. The second paper demonstrates a THz synthesizer using 85GHz CP-PLL and frequency quadrupler with optimal impedance matching technique. The session also includes a digital background calibration LMS technique for a robust wide-band frequency tripler. The fourth paper presents an injection locked frequency tripler with an amplitude detection method to enhance frequency tracking. Lastly, a compact W-band differential doubler is presented with high conversion gain and >36dBc fundamental rejection ratio.
13:30 - 13:50
RTu3A-1 A 116–132GHz -193.6dBc/Hz-FoMT -252.8dB-FoMJ Frequency Synthesizer Using a 114fs-Jitter 60-GHz Double-Sampling PLL with Magnetic Parabolic Tuning and Injection-Locked Frequency Doubler
13:50 - 14:10
RTu3A-2 A 324-to-360-GHz -6-dBm Output Power THz Phase-Locked Loop in 40-nm CMOS
14:10 - 14:30
RTu3A-3 A 28–38GHz Digitally-Assisted Frequency Tripler with Background Calibration in 55nm SiGe BiCMOS
14:30 - 14:50
RTu3A-4 A 35.2–51.4GHz Frequency-Tracking Injection-Locked Frequency Tripler Achieving >28.5dBc Harmonic Rejection Ratios, -7.3dBm Output Power, and 4.3dB Output Power Variation
14:50 - 15:10
RTu3A-5 A High-Conversion-Gain Compact W-Band Distributed Doubler with Second Harmonic Positive Feedback Using Cross-Coupled Capacitor