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Tue 17 Jun | 15:40 - 17:20
207
Innovations in Low-Power, High-Performance Receiver Front-Ends
This session explores cutting-edge techniques for designing high-performance receiver front-ends, focusing on achieving superior sensitivity, linearity, and blocker rejection while minimizing power consumption. The presented papers delve into novel architectures and circuit techniques, including passive filtering, mixer-first topologies, active feedback, and capacitive stacking, pushing the boundaries of receiver performance across various frequency bands.
15:40 - 16:00
RTu4C-1 A 2.4GHz 676µW Receiver Front-End with Passive Analog FIR Filtering Embedded in Down-Converter Achieving >60dB Blocker Rejection
16:00 - 16:20
RTu4C-2 10-to-30-GHz Blocker-Tolerant Mixer-First Receivers with 40-dB/Decade Transition-Band Roll-Off and Maximum 61.7-dB LO-to-RF Isolation
16:20 - 16:40
RTu4C-3 An 11.5mW 12.3–14.5GHz Passive Mixer-First Receiver Front End Achieving 4.2dB NF and -5dBm B1dB
16:40 - 17:00
RTu4C-4 A 4.2dB NF and 39dB Passive Gain Ultra-Low Power Receiver Front-End with an RF-IF Dual-Stage Capacitive Stacking Technique
17:00 - 17:20
RTu4C-5 A 0.2–6GHz 65nm CMOS Active-Feedback LNA with Threefold Balun-Error Correction and Implicit Post-Distortion Technique