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Sun 15 Jun | 08:00 - 17:20
310-311
RF Challenges in the Design and Characterization of Quantum Computing Hardware
This workshop will cover the latest industry developments and research trends in the design, large volume manufacturing, and characterization of superconducting, ion-trap, and semiconductor spin qubits along with the associated quantum processor architectures. We will start with a systematic and comprehensive comparison of the different qubit families, RF hardware realization challenges and their unique features. Presentations will also delve into cryogenic modeling, packaging, on-die small-signal and noise measurements and calibration at microwave and mm-wave frequencies of CMOS and SiGe HBT technologies needed in the control and readout electronics of these qubit families. We will end with the latest examples of such cryogenic control and readout circuits.
08:00 - 17:20
WSO-1 Superconducting Qubits: Wiring up Quantum Entanglement
08:00 - 17:20
WSO-2 Progress in Control Electronics for Scalable Trapped-Ion Quantum Computing
08:00 - 17:20
WSO-3 Circuit Design for Large-Scale Trapped Ions
08:00 - 17:20
WSO-4 Design, Modeling and Control of Spin Silicon Qubits: from Confinement to Characterization
08:00 - 17:20
WSO-5 SiGe HBT Compact Modeling for Circuit Design at Cryogenic Temperatures
08:00 - 17:20
WSO-6 MOSFET Modeling with the sEKV Model for the Design of Cryo-CMOS Circuits
08:00 - 17:20
WSO-7 FDSOI Platform for Quantum Computing
08:00 - 17:20
WSO-9 On-Wafer LNA Noise Measurements for Cryogenic LNAs
08:00 - 17:20
WSO-10 Engineering Quantum Computers for the FTQC Era: A Little About a Lot!
08:00 - 17:20
WSO-11 Progress in Cryogenic Circuits for Superconducting Qubit-Based Quantum Computing