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Tue 9 Jun | 10:10 - 11:50
Room: 254AB
This session explores cutting-edge clock generation architectures achieving sub-30fs jitter and superior spur suppression. The first paper introduces an 8–28GHz DLL with nested feedback to overcome inverter delay limits. The second paper demonstrates a 6.2GHz sampling PLL with 18.2fsrms jitter using bottom-plate sampling. The third paper describes a fractional-N digital PLL reaching 25.4fs jitter via a series-resonance DCO and power-gated oscillator. The fourth paper presents a ring-oscillator clock multiplier using a reference quadrupler for enhanced noise suppression. Finally, the last paper details a 5GHz ring-oscillator PLL employing over-sampling feedforward cancellation for a record -267.05dB FoM.
10:10 - 10:30
Tu2B-1 An 8–28-GHz 16-Phase Delay Locked Loop Employing Nested Feedback Loops in 28-nm CMOS
10:30 - 10:50
Tu2B-2 A 6.2-GHz Reference-Feedthrough-Suppressed Type-I Sampling PLL with a Bottom-Plate-Sampling PD Scoring 18.2 fsrms Jitter, -258.7-dB FoM and -80.6-dBc Reference Spur
10:50 - 11:10
Tu2B-3 A 25.4fs Jitter Fractional-N Digital PLL with an LC-Based Power-Gated Oscillator and Series-Resonance DCO
11:10 - 11:30
Tu2B-4 A 2.4-GHz 168-fsrms-Jitter and -56-dBc-Reference-Spur RO-Based Cascaded Injection-Locked Clock Multiplier
11:30 - 11:50
Tu2B-5 An Ultra Low Noise 5-GHz Ring Oscillator-Based PLL with Over-Sampling Feedforward Phase Noise Cancellation Achieving -267.05dB FoMN