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RMo3A-2: A 16–22GHz Fractional-N PLL in 8nm FinFET with 68 fsrms Jitter
We present a 16–22 GHz low-jitter fractional-N PLL for 5G mm-wave mobile application. It features an integrated low-cost crystal oscillator (XO) reference at 153.6 MHz and a reconfigurable 19-GHz quad...
RMo3A-3: A 210–320GHz Power-Combining Distributed Frequency Doubler with Tuned Pre-Amplification in 0.13µm SiGe BiCMOS
The paper presents the theory and design of a broadband distributed frequency doubler operating across 210–320GHz. We introduce power combining within the distributed structure, with two sets of distr...
RMo3A-4: Design Technology Co-Optimization for RF/mmWave Circuits with Circuit Under Inductor (CUI) in FinFET CMOS Technologies
This paper presents an approach, circuit under inductor (CUI), to reduce chip area as a solution for design technology co-optimization (DTCO) in sub-10-GHz RF and millimeter-wave (mmWave) applications...
RMo3B-1: A 15–50GHz LNA with 2.4dB NF and 25.4±1.4dB Gain in 0.15µm GaAs pHEMT Process
A four-stage ultra-wideband 15–50 GHz LNA in 0.15 µm GaAs pHEMT process is presented in this paper. A RLC feedback with a virtual ground capacitance (RLC & VGC) topology used in current-reuse ...
RMo3B-2: Design of 22.6–29.5/30.4–43.5GHz Dual-Band Low Power LNA with 2.6–3.8dB NF for Millimeter-Wave 5G Applications in 28-nm CMOS
This paper presents a reconfigurable dual-band low power low noise amplifier (LNA) for 5G millimeter-wave (mm-Wave) applications. In the proposed LNA, a two-stage amplifier is designed with wideband i...
RMo3B-3: A 50–68GHz IF Absorptive Receiver with 8-GHz IF-Bandwidth Supporting 16-Channel Carrier-Aggregation and 12Gbps-64QAM Modulation for 5G NR FR2-2 Application
This paper presents a 50–68 GHz IF absorptive receiver. The intermodulation interference caused by IF signal reflection to the mixer is mitigated through absorptive IF amplifier, enabling a wideband a...
RMo3B-4: A 22-to-50GHz Bi-Directional Beamforming CMOS Front-End with Distributed Impedance Reshaping Technique for 5G NR FR2 Applications
This paper presents an ultra-wideband beamforming front-end in 65nm CMOS for n257/n258/n259/n260/ n261/n262 5G FR2 applications. Multiple impedance reshaping techniques are introduced to enable a cont...
RMo3C-1: A 40GS/s 8bit Time-Interleaved Time-Domain ADC Featuring SFDR-Enhanced Sample-and-Hold Circuit and Power-Efficient Adaptive Pulse Generator in 28nm CMOS
This paper reports a 40 GS/s 8b Time-Interleaved (TI) time-domain gated-ring-oscillator analog-to-digital converter (GRO-ADC). The smallest interleaving number of 32 is achieved with a single 8-bit GR...
RMo3C-2: A 12-Bit 6-GS/s Time-Interleaved SAR ADC with On-Chip Mismatch Calibration in 28nm CMOS Technology
This article presents a wideband 12 bit 6 GS/s time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC) implemented in a 28nm CMOS technology addressing FMCW bas...
RMo3C-3: Mostly Digital, Calibration-Free, Band-Pass Delta-Sigma Modulator Using Dual Time-Interleaved Noise-Shaping SAR ADCs
This work presents a highly digital, band-pass delta-sigma modulator (BPDSM) using dual, time-interleaved (TI) noise-shaping successive approximation register (NS-SAR) analog-to-digital converters (AD...