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RTu3A-5: A High-Conversion-Gain Compact W-Band Distributed Doubler with Second Harmonic Positive Feedback Using Cross-Coupled Capacitor
This paper presents a compact and high conversion gain (CG) W-band differential distributed doubler. The proposed two-stage distributed doubler consists of two push-push frequency doublers (PPFDs), ut...
RTu3B-1: A Low-Power D-Band Radar Transceiver with TL-MCR Matching Technique and Output Phase Shifting
This paper proposes a D-band frequency-modulated continuous-wave (FMCW) radar transceiver with two transmitters (TX) and two receivers (RX) fabricated in 28nm CMOS. Transmission-line magnetic-coupled ...
RTu3B-2: A Terahertz FMCW Radar with 169-GHz Synthetic Bandwidth and Reconfigurable Polarization in 40-nm CMOS
The ultra-high-precision wireless sensing capability is in high demanded, but current radars face bandwidth and cost problems. This paper presents a terahertz (THz) ultra-broadband FMCW radar using a ...
RTu3B-3: A 108-to-141.8GHz 27.1%-Tuning-Range Synthesizer Employing a Dual-Reference-FTL Sub-Sampling PLL and 3rd-Harmonic-Enhancement Class-F VCO and Injection-Locked Frequency Tripler
A sub-THz frequency synthesizer employs a cascade of a sub-sampling PLL featuring a frequency-tracking loop with dual co-prime sub-sampling factors for an infinite lock-in range, a 3rd harmonic-amplit...
RTu3B-4: A Fully Integrated 263-GHz Retro-Backscatter Circuit with 105°/82° Reading Angle and 12-dB Conversion Loss
This paper presents the first fully integrated on-chip sub-THz retro-backscatter CMOS circuit, operating at 263 GHz. Using the Van Atta reflector principle and a signal swapping and mode-conversion el...
RTu3B-5: A 127-to-156GHz 64QAM/256QAM Zero-IF CMOS Transceiver Chipset Achieving 42dB IRR and 17.8dBm Output Power
To address the demand for D-band applications requiring massive access with high modulation orders for users, a DC-coupled zero-IF(ZIF) transceiver chipset is proposed in this paper. To enhance the im...
RTu3C-1: A 19.4-fsRMS Jitter 0.1-to-44GHz Cryo-CMOS Fractional-N CP-PLL Featuring Automatic Bleed Calibration for Quantum Computing
This paper presents the first cryogenic fractional-N charge-pump phase-locked loop (CP-PLL) operating at 4K, which can provide ultra-low-jitter clocks for data converters and precisely matched pump so...
RTu3C-2: A Low-Power High-Dynamic-Range Analog Correlator Based on Parametric Multiplication and Integration
This paper presents an analog correlator for radar and communication applications. The proposed correlator leverages a parametric mixer as the RF multiplier core, enabling a high dynamic-range while b...
RTu3C-3: A 204GS/s 1-to-2 Analog Demultiplexer in 22nm FDSOI CMOS
A 204GS/s 1-to-2 analog demultiplexer (ADEMUX) is reported with a measured bandwidth of 60 GHz and a hold-mode isolation > 20 dB up to 67 GHz. It operates with rail-to-rail sampling clock signa...
RTu3C-4: A 224-Gb/s PAM-4 Linear Distributed Driver for Silicon-Photonic Modulators in SiGe BiCMOS
A 224-Gb/s PAM-4 linear distributed driver for silicon-photonic (SiPh) Mach-Zehnder modulators (MZM) is presented in 180-nm SiGe BiCMOS. Equalization is integrated to enhance high-frequency components...