This paper introduces the first fully differential SOI SPDT switch with true dc switching capability combined with broadband RF performance. The design operates from dc to 12 GHz while sustaining ±8 V...
This work presents a 16-phase delay-locked loop operating across 8 to 28 GHz in 28 nm CMOS. The proposed two-stage nested-feedback architecture enables the DLL to overcome the frequency limit set by t...
This paper presents a type-I sampling phase-locked loop (S-PLL) incorporating a bottom-plate sampling phase detector (BPS-PD). The BPS-PD eliminates the input reference to the voltage-controlled oscil...
This work presents a 10-to-12-GHz digital PLL employing a compact series-resonance oscillator to minimize out-of-band phase noise and an LC-based power-gated oscillator to suppress in-band noise and f...
This work presents a low-jitter, low-reference-spur ring oscillator (RO)-based cascaded injection-locked clock multiplier (ILCM). To enhance noise suppression bandwidth, the proposed cascaded ILCM int...
A 5 GHz ring-oscillator-based phase-locked loop (PLL) fabricated in 28 nm CMOS achieves 198.5 fs RMS jitter (1 kHz–100 MHz), -267.05 dB normalized jitter-power figure of merit, and -247.05 dB figure o...
This work proposes a low-loss digital-step attenuator (DSA) that covers the entire D-band (110–170 GHz) with a tuning range of 15.5 dB and a step of 0.5 dB. Utilizing a multi-stage reflective-type att...
This paper presents a low-noise amplifier (LNA) that achieves dual-band operation by employing a cascaded single-path and dual-mode gain-boosting amplifier core. The proposed LNA selectively amplifies...
This paper presents a high-power second-harmonic voltage-control oscillator (VCO) utilizing the deep-triode-induced current top-clipping (DT-CTC) technique. By employing a cascode topology featuring a...
A sub-THz VCO employs hybrid tuning techniques to achieve ultra-wide frequency tuning range with high Qtank and low phase noise. Coarse magnetic tuning features a compact 12-section 3-layer stacked tr...